In the manufacture of integrated circuits, a commonly used practice is to form silicide on source/drain regions and on polysilicon gates. This practice has become increasingly important for very high-density devices where the feature size is reduced to a fraction of a micrometer. Silicide provides good ohmic contact, reduces the sheet resistivity of source/drain regions and polysilicon gates, increases the effective contact area, and provides an etch stop.
A common technique employed in the semiconductor manufacturing industry is self-aligned silicide ("salicide") processing. Salicide processing involves the deposition of a metal that forms intermetallic with silicon (Si), but does not react with silicon oxide or silicon nitride. Common metals employed in salicide processing are titanium (Ti), cobalt (Co), and nickel (Ni). These common metals form low resistivity phases with silicon, such as TiSi.sub.2, CoSi.sub.2 and NiSi. The metal is deposited with a uniform thickness across the entire semiconductor wafer. This is accomplished using, for example, physical vapor deposition (PVD) from an ultra-pure sputtering target and a commercially available ultra-high vacuum (UHV), multi-chamber, DC magnetron sputtering system. Deposition is performed after both gate etch and source/drain junction formation. After deposition, the metal blankets the polysilicon gate electrode, the oxide spacers, the oxide isolation, and the exposed electrodes. A cross-section of an exemplary semiconductor wafer during one stage of a salicide formation process in accordance with the prior art techniques is depicted in FIG. 1.
As shown in FIG. 1, a silicon substrate 10 has been provided with the source/drain junctions 12, 14 and a polysilicon gate 16. Oxide spacers 18 have been formed on the sides of the polysilicon gate 16. Metal silicide regions 20, comprising cobalt silicide, for example, have been formed on the source/drain junctions 12, 14, the polysilicon gate 16.
To form the metal suicide regions 20, a refractory metal layer is deposited over the device. A first rapid thermal anneal (RTA) step is then performed at a temperature of between about 450.degree.-700.degree. C. for a short period of time in a nitrogen atmosphere. The nitrogen reacts with the metal to form a metal nitride at the surface of the metal, while the metal reacts with silicon and forms silicide in those regions where it comes in direct contact with the silicon.
After the first rapid thermal anneal step, any metal that is unreacted is stripped away using a wet etch process that is selective to the silicide. A second, higher temperature rapid thermal anneal step, for example above 700.degree. C., is applied to form a lower resistance silicide phase of the metal silicide. The resultant structure is depicted in FIG. 1 in which the higher resistivity metal silicide has been transformed to the lowest resistivity phase metal silicide. For example, when the metal is cobalt, the higher resistivity phase is CoSi and the lowest resistivity phase is CoSi.sub.2. When the polysilicon and diffusion patterns are both exposed to the metal, the silicide forms simultaneously over both regions so that this method is described as "salicide" since the silicides formed over the polysilicon and single-crystal silicon are self-aligned to each other.
Titanium is currently the most prevalent metal used for salicide processing in the integrated circuit industry, largely because titanium is already employed in other areas of 0.5 micron CMOS logic technologies. In the first rapid thermal anneal step, the so-called "C49" crystallographic titanium phase is formed, and the lower resistance "C54" phase forms during the second rapid thermal anneal step. However, the titanium silicide sheet resistance rises dramatically due to narrow-line effects. This is described in European Publication No. 0651076. Cobalt silicide (CoSi.sub.2) has been introduced by several integrated circuit manufacturers as the replacement for titanium silicide. Since cobalt silicide forms by a diffusion reaction, it does not display the narrow-line effects observed with titanium silicide that forms by nucleation-and-growth. Some of the other advantages of cobalt over alternative materials such as nickel, platinum, or palladium are that cobalt silicide provides low resistivity, allows lower-temperature processing, and has a reduced tendency for forming diode-like interfaces.
Another important advantage of cobalt silicide over titanium silicide is the improvement that cobalt silicide provides in transistor drain saturation current (Idsat). This is a measure of how fast a transistor is able to turn on. The drain saturation current is improved because the cobalt silicide is normally thinner than conventional titanium silicide on the source/drain areas so that the cobalt silicide will contact the source/drain areas at a region of higher dopant concentration. FIG. 2 is a plot of a source/drain junction doping concentration as it varies with the source/drain junction depth in a conventionally doped device. As seen in FIG. 2, the source/drain junction depth, plotted on the X-axis, shows the depth of titanium silicide being greater then the depth of cobalt silicide within the source/drain junction. Hence, the bottom of the cobalt silicide contacts the source/drain junction at a point 30 of higher dopant concentration than the point 32 of lower dopant concentration.
Since the cobalt silicide is thinner than conventional titanium silicide on the source/drain areas and contacts the source/drain area at a region of higher doping area, the contact resistance (Rc) is lower when cobalt silicide is employed. This contributes to a lower overall transistor turn-on resistance. Improvement in the technology operating speed is provided when the overall transistor turn-on resistance is lowered.
The use of a thinner cobalt silicide, instead of titanium silicide, tends to lead to a higher sheet resistance (Rs) than a thicker film would. Higher sheet resistance degrades the technology operating speed. Making the cobalt silicide thicker would lower the sheet resistance (Rs). However, this presents a problem in that thickening the silicide while using a conventionally doped junction causes the contact resistance (Rc) to increase. As can be seen from FIG. 2, the source/drain dopant implant is traditionally peaked at the surface to maintain the junction at a shallow depth in order to minimize short channel effects. A thicker cobalt silicide film therefore will make contact at a region of lower doping, similar to the titanium silicide, resulting in a higher contact resistance (Rc).